Datasets:

HPAI-BSC
/

SystemVerilog-RL-12k

prompt stringlengths 1.39k 54.7k	top_module stringlengths 1 83	instance stringlengths 2 89	mutations listlengths 0 20
"You are an expert SystemVerilog verification engineer. Below is a stimulus testbench for `mem_wb_pi(...TRUNCATED)	mem_wb_pipeline_reg	tb	["/* Generated by Yosys 0.64+215 (git sha1 54866d154-dirty, aarch64-apple-darwin23.5-clang++ 18.1.8 (...TRUNCATED)
"You are an expert SystemVerilog verification engineer. The SystemVerilog module below is a stimulus(...TRUNCATED)	barrel_shifter	tb_barrel_shifter	["/* Generated by Yosys 0.64+215 (git sha1 54866d154-dirty, aarch64-apple-darwin23.5-clang++ 18.1.8 (...TRUNCATED)
"You are an expert SystemVerilog verification engineer. The SystemVerilog module below is a stimulus(...TRUNCATED)	Example	tb_Example	["/* Generated by Yosys 0.64+215 (git sha1 54866d154-dirty, aarch64-apple-darwin23.5-clang++ 18.1.8 (...TRUNCATED)
"You are an expert SystemVerilog verification engineer. Write a complete, self-checking SystemVerilo(...TRUNCATED)	pzbcm_async_fifo_reset_sync	pzbcm_async_fifo_reset_sync_test	["/* Generated by Yosys 0.64+215 (git sha1 54866d154-dirty, aarch64-apple-darwin23.5-clang++ 18.1.8 (...TRUNCATED)
"You are an expert SystemVerilog verification engineer. The testbench for `alu_4bit` shown below has(...TRUNCATED)	alu_4bit	testbench	["/* Generated by Yosys 0.64+215 (git sha1 54866d154-dirty, aarch64-apple-darwin23.5-clang++ 18.1.8 (...TRUNCATED)
"You are an expert SystemVerilog verification engineer. Write a complete, self-checking SystemVerilo(...TRUNCATED)	FC	FC_verif_tb	[]
"You are an expert SystemVerilog verification engineer. The SystemVerilog module below is a stimulus(...TRUNCATED)	top	tb_top	["/* Generated by Yosys 0.64+215 (git sha1 54866d154-dirty, aarch64-apple-darwin23.5-clang++ 18.1.8 (...TRUNCATED)
"Read the SystemVerilog module `tt_um_CLA8` below and write a complete self-checking SystemVerilog t(...TRUNCATED)	tt_um_CLA8	tb_tt_um_CLA8	["/* Generated by Yosys 0.64+215 (git sha1 54866d154-dirty, aarch64-apple-darwin23.5-clang++ 18.1.8 (...TRUNCATED)
"You are an expert SystemVerilog verification engineer. Write a complete, self-checking SystemVerilo(...TRUNCATED)	lms_ctr_mm_interconnect_0_router_005	lms_ctr_mm_interconnect_0_router_005_tb	["/* Generated by Yosys 0.64+215 (git sha1 54866d154-dirty, aarch64-apple-darwin23.5-clang++ 18.1.8 (...TRUNCATED)
"You are an expert SystemVerilog verification engineer. Convert the stimulus-only testbench below in(...TRUNCATED)	ngs_boot_core_mm_interconnect_0_avalon_st_adapter_003_error_adapter_0	tb_ngs_boot_core_mm_interconnect_0_avalon_st_adapter_003_error_adapter_0	["/* Generated by Yosys 0.64+215 (git sha1 54866d154-dirty, aarch64-apple-darwin23.5-clang++ 18.1.8 (...TRUNCATED)

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SystemVerilog RL

An RL dataset for SystemVerilog verification tasks. For each row, we ask the model to produce a self-checking testbench; a good testbench must pass on the golden design and fail on the mutants.

The dataset contains 11,902 problems, with up to 20 Yosys-generated netlist mutations per problem.

🤗 Models

🤗 Datasets

SystemVerilog-SFT-86k
SystemVerilog-RL-12k ← you are here

Structure

Each line of train.jsonl contains four fields, in this order:

Field	Description
`prompt`	Task to generate a self-checking testbench or add checking logic to an existing stimulus testbench.
`top_module`	DUT module name.
`instance`	Testbench module name used by the simulation harness.
`mutations`	Mutated DUT sources for reward evaluation; keep these out of model inputs.

Derived from

RTL snippets collected from The Stack v1, The Stack v2, MetRex, and our GitHub crawl, together with Tiny Tapeout designs. We construct two types of RL tasks:

Stimulus generation: problems where the Gemma-4-31B teacher failed to produce a passing testbench. The model is asked to generate a self-checking testbench for these problems.
Checking generation: successful examples sampled from the SFT dataset. We use the teacher to strip the checking logic from their testbenches, then ask the model to add that logic back.

Task source	Problems
Stimulus generation	6,736
Functional checking	4,519
Tiny Tapeout	647
Total	11,902

Decontamination

The dataset was decontaminated against VerilogEval v2.0, RTLLM v2.1, and CVDP v1.1.0 Heavy Agentic tasks, harnesses, and public RTL repository context, using normalized exact and fuzzy code matching, with prompts and descriptions checked separately.