phanerozoic/Coq-CompCert · Datasets at Hugging Face

fact stringlengths 7 4.84k	type stringclasses 18 values	library stringclasses 14 values	imports listlengths 0 27	filename stringclasses 205 values	symbolic_name stringlengths 1 49	docstring stringlengths 6 2.5k ⌀
eval_shl: binary_constructor_sound shl Val.shl.	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_shl	General shifts
eval_shr: binary_constructor_sound shr Val.shr.	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_shr	null
eval_shru: binary_constructor_sound shru Val.shru.	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_shru	null
eval_negf: unary_constructor_sound negf Val.negf.	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_negf	Floating-point operations
eval_absf: unary_constructor_sound absf Val.absf.	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_absf	null
eval_addf: binary_constructor_sound addf Val.addf.	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_addf	null
eval_subf: binary_constructor_sound subf Val.subf.	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_subf	null
eval_mulf: binary_constructor_sound mulf Val.mulf.	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_mulf	null
eval_negfs: unary_constructor_sound negfs Val.negfs.	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_negfs	null
eval_absfs: unary_constructor_sound absfs Val.absfs.	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_absfs	null
eval_addfs: binary_constructor_sound addfs Val.addfs.	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_addfs	null
eval_subfs: binary_constructor_sound subfs Val.subfs.	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_subfs	null
eval_mulfs: binary_constructor_sound mulfs Val.mulfs.	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_mulfs	null
eval_compimm: forall le c a n2 x, eval_expr ge sp e m le a x -> exists v, eval_expr ge sp e m le (compimm default intsem c a n2) v /\ Val.lessdef (sem c x (Vint n2)) v.	Lemma	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_compimm	null
eval_compimm_swap: forall le c a n2 x, eval_expr ge sp e m le a x -> exists v, eval_expr ge sp e m le (compimm default intsem (swap_comparison c) a n2) v /\ Val.lessdef (sem c (Vint n2) x) v.	Lemma	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_compimm_swap	null
eval_comp: forall c, binary_constructor_sound (comp c) (Val.cmp c).	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_comp	null
eval_compu: forall c, binary_constructor_sound (compu c) (Val.cmpu (Mem.valid_pointer m) c).	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_compu	null
eval_compf: forall c, binary_constructor_sound (compf c) (Val.cmpf c).	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_compf	null
eval_compfs: forall c, binary_constructor_sound (compfs c) (Val.cmpfs c).	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_compfs	null
eval_singleoffloat: unary_constructor_sound singleoffloat Val.singleoffloat.	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_singleoffloat	Floating-point conversions
eval_floatofsingle: unary_constructor_sound floatofsingle Val.floatofsingle.	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_floatofsingle	null
eval_intoffloat: forall le a x y, eval_expr ge sp e m le a x -> Val.intoffloat x = Some y -> exists v, eval_expr ge sp e m le (intoffloat a) v /\ Val.lessdef y v.	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_intoffloat	null
eval_floatofint: forall le a x y, eval_expr ge sp e m le a x -> Val.floatofint x = Some y -> exists v, eval_expr ge sp e m le (floatofint a) v /\ Val.lessdef y v.	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_floatofint	null
eval_intuoffloat: forall le a x y, eval_expr ge sp e m le a x -> Val.intuoffloat x = Some y -> exists v, eval_expr ge sp e m le (intuoffloat a) v /\ Val.lessdef y v.	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_intuoffloat	null
eval_floatofintu: forall le a x y, eval_expr ge sp e m le a x -> Val.floatofintu x = Some y -> exists v, eval_expr ge sp e m le (floatofintu a) v /\ Val.lessdef y v.	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_floatofintu	null
eval_intofsingle: forall le a x y, eval_expr ge sp e m le a x -> Val.intofsingle x = Some y -> exists v, eval_expr ge sp e m le (intofsingle a) v /\ Val.lessdef y v.	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_intofsingle	null
eval_singleofint: forall le a x y, eval_expr ge sp e m le a x -> Val.singleofint x = Some y -> exists v, eval_expr ge sp e m le (singleofint a) v /\ Val.lessdef y v.	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_singleofint	null
eval_intuofsingle: forall le a x y, eval_expr ge sp e m le a x -> Val.intuofsingle x = Some y -> exists v, eval_expr ge sp e m le (intuofsingle a) v /\ Val.lessdef y v.	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_intuofsingle	null
eval_singleofintu: forall le a x y, eval_expr ge sp e m le a x -> Val.singleofintu x = Some y -> exists v, eval_expr ge sp e m le (singleofintu a) v /\ Val.lessdef y v.	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_singleofintu	null
eval_select: forall le ty cond al vl a1 v1 a2 v2, select_supported ty = true -> eval_exprlist ge sp e m le al vl -> eval_expr ge sp e m le a1 v1 -> eval_expr ge sp e m le a2 v2 -> exists v, eval_expr ge sp e m le (select ty cond al a1 a2) v /\ Val.lessdef (Val.select (eval_condition cond vl m) v1 v2 ty) v.	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_select	Selection
eval_addressing: forall le chunk a v b ofs, eval_expr ge sp e m le a v -> v = Vptr b ofs -> match addressing chunk a with (mode, args) => exists vl, eval_exprlist ge sp e m le args vl /\ eval_addressing ge sp mode vl = Some v end.	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_addressing	Addressing modes
eval_builtin_arg: forall a v, eval_expr ge sp e m nil a v -> CminorSel.eval_builtin_arg ge sp e m (builtin_arg a) v.	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_builtin_arg	Builtins
eval_platform_builtin: forall bf al a vl v le, platform_builtin bf al = Some a -> eval_exprlist ge sp e m le al vl -> platform_builtin_sem bf vl = Some v -> exists v', eval_expr ge sp e m le a v' /\ Val.lessdef v v'.	Theorem	aarch64	[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]	aarch64/SelectOpproof.v	eval_platform_builtin	Platform-specific known builtins
fe_ofs_arg := 0.	Definition	aarch64	[ "Coqlib", "AST", "Memory", "Separation", "Bounds" ]	aarch64/Stacklayout.v	fe_ofs_arg	The general shape of activation records is as follows, from bottom (lowest offsets) to top: - Space for outgoing arguments to function calls. - Back link to parent frame - Return address - Saved values of callee-save registers used by the function. - Local stack slots. - Space for the stack-allocated data declared in Cminor. The stack pointer is kept 16-aligned.
make_env (b: bounds) : frame_env := let olink := align (4 * b.(bound_outgoing)) 8 in (* back link ) let oretaddr := olink + 8 in ( return address ) let ocs := oretaddr + 8 in ( callee-saves ) let ol := align (size_callee_save_area b ocs) 8 in ( locals ) let ostkdata := align (ol + 4 b.(bound_local)) 8 in (* stack data *) let sz := align (ostkdata + b.(bound_stack_data)) 16 in {\| fe_size := sz; fe_ofs_link := olink; fe_ofs_retaddr := oretaddr; fe_ofs_local := ol; fe_ofs_callee_save := ocs; fe_stack_data := ostkdata; fe_used_callee_save := b.(used_callee_save) \|}.	Definition	aarch64	[ "Coqlib", "AST", "Memory", "Separation", "Bounds" ]	aarch64/Stacklayout.v	make_env	null
frame_env_separated: forall b sp m P, let fe := make_env b in m \|= range sp 0 (fe_stack_data fe) range sp (fe_stack_data fe + bound_stack_data b) (fe_size fe) P -> m \|= range sp (fe_ofs_local fe) (fe_ofs_local fe + 4 * bound_local b) ** range sp fe_ofs_arg (fe_ofs_arg + 4 * bound_outgoing b) range sp (fe_ofs_link fe) (fe_ofs_link fe + size_chunk Mptr) range sp (fe_ofs_retaddr fe) (fe_ofs_retaddr fe + size_chunk Mptr) range sp (fe_ofs_callee_save fe) (size_callee_save_area b (fe_ofs_callee_save fe)) P.	Lemma	aarch64	[ "Coqlib", "AST", "Memory", "Separation", "Bounds" ]	aarch64/Stacklayout.v	frame_env_separated	null
frame_env_range: forall b, let fe := make_env b in 0 <= fe_stack_data fe /\ fe_stack_data fe + bound_stack_data b <= fe_size fe.	Lemma	aarch64	[ "Coqlib", "AST", "Memory", "Separation", "Bounds" ]	aarch64/Stacklayout.v	frame_env_range	null
frame_env_aligned: forall b, let fe := make_env b in (8 \| fe_ofs_arg) /\ (8 \| fe_ofs_local fe) /\ (8 \| fe_stack_data fe) /\ (align_chunk Mptr \| fe_ofs_link fe) /\ (align_chunk Mptr \| fe_ofs_retaddr fe).	Lemma	aarch64	[ "Coqlib", "AST", "Memory", "Separation", "Bounds" ]	aarch64/Stacklayout.v	frame_env_aligned	null
eval_static_shift (s: shift) (v: aval) (n: amount32) : aval := match s with \| Slsl => shl v (I n) \| Slsr => shru v (I n) \| Sasr => shr v (I n) \| Sror => ror v (I n) end.	Definition	aarch64	[ "Coqlib", "Compopts", "AST", "Integers", "Floats", "Values", "Memory", "Globalenvs", "Op", "RTL", "ValueDomain" ]	aarch64/ValueAOp.v	eval_static_shift	Value analysis for AArch64 operators
eval_static_shiftl (s: shift) (v: aval) (n: amount64) : aval := match s with \| Slsl => shll v (I n) \| Slsr => shrlu v (I n) \| Sasr => shrl v (I n) \| Sror => rorl v (I n) end.	Definition	aarch64	[ "Coqlib", "Compopts", "AST", "Integers", "Floats", "Values", "Memory", "Globalenvs", "Op", "RTL", "ValueDomain" ]	aarch64/ValueAOp.v	eval_static_shiftl	null
eval_static_extend (x: extension) (v: aval) (n: amount64) : aval := shll (match x with Xsgn32 => longofint v \| Xuns32 => longofintu v end) (I n).	Definition	aarch64	[ "Coqlib", "Compopts", "AST", "Integers", "Floats", "Values", "Memory", "Globalenvs", "Op", "RTL", "ValueDomain" ]	aarch64/ValueAOp.v	eval_static_extend	null
eval_static_condition (cond: condition) (vl: list aval): abool := match cond, vl with \| Ccomp c, v1 :: v2 :: nil => cmp_bool c v1 v2 \| Ccompu c, v1 :: v2 :: nil => cmpu_bool c v1 v2 \| Ccompimm c n, v1 :: nil => cmp_bool c v1 (I n) \| Ccompuimm c n, v1 :: nil => cmpu_bool c v1 (I n) \| Ccompshift c s a, v1 :: v2 :: nil => cmp_bool c v1 (eval_static_shift s v2 a) \| Ccompushift c s a, v1 :: v2 :: nil => cmpu_bool c v1 (eval_static_shift s v2 a) \| Cmaskzero m, v1 :: nil => maskzero v1 m \| Cmasknotzero m, v1 :: nil => cnot (maskzero v1 m) \| Ccompl c, v1 :: v2 :: nil => cmpl_bool c v1 v2 \| Ccomplu c, v1 :: v2 :: nil => cmplu_bool c v1 v2 \| Ccomplimm c n, v1 :: nil => cmpl_bool c v1 (L n) \| Ccompluimm c n, v1 :: nil => cmplu_bool c v1 (L n) \| Ccomplshift c s a, v1 :: v2 :: nil => cmpl_bool c v1 (eval_static_shiftl s v2 a) \| Ccomplushift c s a, v1 :: v2 :: nil => cmplu_bool c v1 (eval_static_shiftl s v2 a) \| Cmasklzero m, v1 :: nil => cmpl_bool Ceq (andl v1 (L m)) (L Int64.zero) \| Cmasklnotzero m, v1 :: nil => cmpl_bool Cne (andl v1 (L m)) (L Int64.zero) \| Ccompf c, v1 :: v2 :: nil => cmpf_bool c v1 v2 \| Cnotcompf c, v1 :: v2 :: nil => cnot (cmpf_bool c v1 v2) \| Ccompfzero c, v1 :: nil => cmpf_bool c v1 (F Float.zero) \| Cnotcompfzero c, v1 :: nil => cnot (cmpf_bool c v1 (F Float.zero)) \| Ccompfs c, v1 :: v2 :: nil => cmpfs_bool c v1 v2 \| Cnotcompfs c, v1 :: v2 :: nil => cnot (cmpfs_bool c v1 v2) \| Ccompfszero c, v1 :: nil => cmpfs_bool c v1 (FS Float32.zero) \| Cnotcompfszero c, v1 :: nil => cnot (cmpfs_bool c v1 (FS Float32.zero)) \| _, _ => Bnone end.	Definition	aarch64	[ "Coqlib", "Compopts", "AST", "Integers", "Floats", "Values", "Memory", "Globalenvs", "Op", "RTL", "ValueDomain" ]	aarch64/ValueAOp.v	eval_static_condition	null
eval_static_addressing (addr: addressing) (vl: list aval): aval := match addr, vl with \| Aindexed n, v1 :: nil => addl v1 (L n) \| Aindexed2, v1 :: v2 :: nil => addl v1 v2 \| Aindexed2shift a, v1 :: v2 :: nil => addl v1 (shll v2 (I a)) \| Aindexed2ext x a, v1 :: v2 :: nil => addl v1 (eval_static_extend x v2 a) \| Aglobal s ofs, nil => Ptr (Gl s ofs) \| Ainstack ofs, nil => Ptr (Stk ofs) \| _, _ => Vbot end.	Definition	aarch64	[ "Coqlib", "Compopts", "AST", "Integers", "Floats", "Values", "Memory", "Globalenvs", "Op", "RTL", "ValueDomain" ]	aarch64/ValueAOp.v	eval_static_addressing	null
eval_static_operation (op: operation) (vl: list aval): aval := match op, vl with \| Omove, v1::nil => v1 \| Ointconst n, nil => I n \| Olongconst n, nil => L n \| Ofloatconst n, nil => if propagate_float_constants tt then F n else ntop \| Osingleconst n, nil => if propagate_float_constants tt then FS n else ntop \| Oaddrsymbol id ofs, nil => Ptr (Gl id ofs) \| Oaddrstack ofs, nil => Ptr (Stk ofs) \| Oshift s a, v1::nil => eval_static_shift s v1 a \| Oadd, v1::v2::nil => add v1 v2 \| Oaddshift s a, v1::v2::nil => add v1 (eval_static_shift s v2 a) \| Oaddimm n, v1::nil => add v1 (I n) \| Oneg, v1::nil => neg v1 \| Onegshift s a, v1::nil => neg (eval_static_shift s v1 a) \| Osub, v1::v2::nil => sub v1 v2 \| Osubshift s a, v1::v2::nil => sub v1 (eval_static_shift s v2 a) \| Omul, v1::v2::nil => mul v1 v2 \| Omuladd, v1::v2::v3::nil => add v1 (mul v2 v3) \| Omulsub, v1::v2::v3::nil => sub v1 (mul v2 v3) \| Odiv, v1::v2::nil => divs v1 v2 \| Odivu, v1::v2::nil => divu v1 v2 \| Oand, v1::v2::nil => and v1 v2 \| Oandshift s a, v1::v2::nil => and v1 (eval_static_shift s v2 a) \| Oandimm n, v1::nil => and v1 (I n) \| Oor, v1::v2::nil => or v1 v2 \| Oorshift s a, v1::v2::nil => or v1 (eval_static_shift s v2 a) \| Oorimm n, v1::nil => or v1 (I n) \| Oxor, v1::v2::nil => xor v1 v2 \| Oxorshift s a, v1::v2::nil => xor v1 (eval_static_shift s v2 a) \| Oxorimm n, v1::nil => xor v1 (I n) \| Onot, v1::nil => notint v1 \| Onotshift s a, v1::nil => notint (eval_static_shift s v1 a) \| Obic, v1::v2::nil => and v1 (notint v2) \| Obicshift s a, v1::v2::nil => and v1 (notint (eval_static_shift s v2 a)) \| Oorn, v1::v2::nil => or v1 (notint v2) \| Oornshift s a, v1::v2::nil => or v1 (notint (eval_static_shift s v2 a)) \| Oeqv, v1::v2::nil => xor v1 (notint v2) \| Oeqvshift s a, v1::v2::nil => xor v1 (notint (eval_static_shift s v2 a)) \| Oshl, v1::v2::nil => shl v1 v2 \| Oshr, v1::v2::nil => shr v1 v2 \| Oshru, v1::v2::nil => shru v1 v2 \| Oshrximm n, v1::nil => shrx v1 (I n) \| Ozext s, v1::nil => zero_ext s v1 \| Osext s, v1::nil => sign_ext s v1 \| Oshlzext s a, v1::nil => shl (zero_ext s v1) (I a) \| Oshlsext s a, v1::nil => shl (sign_ext s v1) (I a) \| Ozextshr a s, v1::nil => zero_ext s (shru v1 (I a)) \| Osextshr a s, v1::nil => sign_ext s (shr v1 (I a)) \| Oshiftl s a, v1::nil => eval_static_shiftl s v1 a \| Oextend x a, v1::nil => eval_static_extend x v1 a ...	Definition	aarch64	[ "Coqlib", "Compopts", "AST", "Integers", "Floats", "Values", "Memory", "Globalenvs", "Op", "RTL", "ValueDomain" ]	aarch64/ValueAOp.v	eval_static_operation	null
eval_static_shift_sound: forall v av s n, vmatch bc v av -> vmatch bc (eval_shift s v n) (eval_static_shift s av n).	Lemma	aarch64	[ "Coqlib", "Compopts", "AST", "Integers", "Floats", "Values", "Memory", "Globalenvs", "Op", "RTL", "ValueDomain" ]	aarch64/ValueAOp.v	eval_static_shift_sound	null
eval_static_shiftl_sound: forall v av s n, vmatch bc v av -> vmatch bc (eval_shiftl s v n) (eval_static_shiftl s av n).	Lemma	aarch64	[ "Coqlib", "Compopts", "AST", "Integers", "Floats", "Values", "Memory", "Globalenvs", "Op", "RTL", "ValueDomain" ]	aarch64/ValueAOp.v	eval_static_shiftl_sound	null
eval_static_extend_sound: forall v av x n, vmatch bc v av -> vmatch bc (eval_extend x v n) (eval_static_extend x av n).	Lemma	aarch64	[ "Coqlib", "Compopts", "AST", "Integers", "Floats", "Values", "Memory", "Globalenvs", "Op", "RTL", "ValueDomain" ]	aarch64/ValueAOp.v	eval_static_extend_sound	null
eval_static_condition_sound: forall cond vargs m aargs, list_forall2 (vmatch bc) vargs aargs -> cmatch (eval_condition cond vargs m) (eval_static_condition cond aargs).	Theorem	aarch64	[ "Coqlib", "Compopts", "AST", "Integers", "Floats", "Values", "Memory", "Globalenvs", "Op", "RTL", "ValueDomain" ]	aarch64/ValueAOp.v	eval_static_condition_sound	null
symbol_address_sound: forall id ofs, vmatch bc (Genv.symbol_address ge id ofs) (Ptr (Gl id ofs)).	Lemma	aarch64	[ "Coqlib", "Compopts", "AST", "Integers", "Floats", "Values", "Memory", "Globalenvs", "Op", "RTL", "ValueDomain" ]	aarch64/ValueAOp.v	symbol_address_sound	null
symbol_address_sound_2: forall id ofs, vmatch bc (Genv.symbol_address ge id ofs) (Ifptr (Gl id ofs)).	Lemma	aarch64	[ "Coqlib", "Compopts", "AST", "Integers", "Floats", "Values", "Memory", "Globalenvs", "Op", "RTL", "ValueDomain" ]	aarch64/ValueAOp.v	symbol_address_sound_2	null
eval_static_addressing_sound: forall addr vargs vres aargs, eval_addressing ge (Vptr sp Ptrofs.zero) addr vargs = Some vres -> list_forall2 (vmatch bc) vargs aargs -> vmatch bc vres (eval_static_addressing addr aargs).	Theorem	aarch64	[ "Coqlib", "Compopts", "AST", "Integers", "Floats", "Values", "Memory", "Globalenvs", "Op", "RTL", "ValueDomain" ]	aarch64/ValueAOp.v	eval_static_addressing_sound	null
eval_static_operation_sound: forall op vargs m vres aargs, eval_operation ge (Vptr sp Ptrofs.zero) op vargs m = Some vres -> list_forall2 (vmatch bc) vargs aargs -> vmatch bc vres (eval_static_operation op aargs).	Theorem	aarch64	[ "Coqlib", "Compopts", "AST", "Integers", "Floats", "Values", "Memory", "Globalenvs", "Op", "RTL", "ValueDomain" ]	aarch64/ValueAOp.v	eval_static_operation_sound	null
ptr64 := false.	Definition	arm	[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]	arm/Archi.v	ptr64	null
big_endian: bool.	Parameter	arm	[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]	arm/Archi.v	big_endian	null
align_int64 := 8%Z.	Definition	arm	[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]	arm/Archi.v	align_int64	null
align_float64 := 8%Z.	Definition	arm	[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]	arm/Archi.v	align_float64	null
splitlong := true.	Definition	arm	[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]	arm/Archi.v	splitlong	null
splitlong_ptr32: splitlong = true -> ptr64 = false.	Lemma	arm	[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]	arm/Archi.v	splitlong_ptr32	null
default_nan_64 := (false, iter_nat 51 _ xO xH).	Definition	arm	[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]	arm/Archi.v	default_nan_64	null
default_nan_32 := (false, iter_nat 22 _ xO xH).	Definition	arm	[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]	arm/Archi.v	default_nan_32	null
choose_nan (is_signaling: positive -> bool) (default: bool * positive) (l0: list (bool * positive)) : bool * positive := let fix choose_snan (l1: list (bool * positive)) := match l1 with \| nil => match l0 with nil => default \| n :: _ => n end \| ((s, p) as n) :: l1 => if is_signaling p then n else choose_snan l1 end in choose_snan l0.	Definition	arm	[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]	arm/Archi.v	choose_nan	Choose the first signaling NaN, if any; otherwise choose the first NaN; otherwise use default.
choose_nan_idem: forall is_signaling default n, choose_nan is_signaling default (n :: n :: nil) = choose_nan is_signaling default (n :: nil).	Lemma	arm	[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]	arm/Archi.v	choose_nan_idem	null
choose_nan_64 := choose_nan (fun p => negb (Pos.testbit p 51)) default_nan_64.	Definition	arm	[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]	arm/Archi.v	choose_nan_64	null
choose_nan_32 := choose_nan (fun p => negb (Pos.testbit p 22)) default_nan_32.	Definition	arm	[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]	arm/Archi.v	choose_nan_32	null
choose_nan_64_idem: forall n, choose_nan_64 (n :: n :: nil) = choose_nan_64 (n :: nil).	Lemma	arm	[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]	arm/Archi.v	choose_nan_64_idem	null
choose_nan_32_idem: forall n, choose_nan_32 (n :: n :: nil) = choose_nan_32 (n :: nil).	Lemma	arm	[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]	arm/Archi.v	choose_nan_32_idem	null
fma_order {A: Type} (x y z: A) := (z, x, y).	Definition	arm	[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]	arm/Archi.v	fma_order	null
fma_invalid_mul_is_nan := true.	Definition	arm	[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]	arm/Archi.v	fma_invalid_mul_is_nan	null
float_of_single_preserves_sNaN := false.	Definition	arm	[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]	arm/Archi.v	float_of_single_preserves_sNaN	null
float_conversion_default_nan := false.	Definition	arm	[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]	arm/Archi.v	float_conversion_default_nan	null
abi_kind := Softfloat \| Hardfloat.	Inductive	arm	[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]	arm/Archi.v	abi_kind	Which ABI to use: either the standard ARM EABI with floats passed in integer registers, or the "hardfloat" variant of the EABI that uses FP registers instead.
abi: abi_kind.	Parameter	arm	[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]	arm/Archi.v	abi	null
thumb2_support: bool.	Parameter	arm	[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]	arm/Archi.v	thumb2_support	Whether instructions added with Thumb2 are supported. True for ARMv6T2 and above.
hardware_idiv : unit -> bool.	Parameter	arm	[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]	arm/Archi.v	hardware_idiv	Whether the hardware supports sdiv and udiv
ireg: Type := \| IR0: ireg \| IR1: ireg \| IR2: ireg \| IR3: ireg \| IR4: ireg \| IR5: ireg \| IR6: ireg \| IR7: ireg \| IR8: ireg \| IR9: ireg \| IR10: ireg \| IR11: ireg \| IR12: ireg \| IR13: ireg \| IR14: ireg.	Inductive	arm	[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]	arm/Asm.v	ireg	Integer registers, floating-point registers.
freg: Type := \| FR0: freg \| FR1: freg \| FR2: freg \| FR3: freg \| FR4: freg \| FR5: freg \| FR6: freg \| FR7: freg \| FR8: freg \| FR9: freg \| FR10: freg \| FR11: freg \| FR12: freg \| FR13: freg \| FR14: freg \| FR15: freg.	Inductive	arm	[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]	arm/Asm.v	freg	null
sreg: Type := \| SR0: sreg \| SR1: sreg \| SR2: sreg \| SR3: sreg \| SR4: sreg \| SR5: sreg \| SR6: sreg \| SR7: sreg \| SR8: sreg \| SR9: sreg \| SR10: sreg \| SR11: sreg \| SR12: sreg \| SR13: sreg \| SR14: sreg \| SR15: sreg \| SR16: sreg \| SR17: sreg \| SR18: sreg \| SR19: sreg \| SR20: sreg \| SR21: sreg \| SR22: sreg \| SR23: sreg \| SR24: sreg \| SR25: sreg \| SR26: sreg \| SR27: sreg \| SR28: sreg \| SR29: sreg \| SR30: sreg \| SR31: sreg.	Inductive	arm	[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]	arm/Asm.v	sreg	null
ireg_eq: forall (x y: ireg), {x=y} + {x<>y}.	Lemma	arm	[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]	arm/Asm.v	ireg_eq	null
freg_eq: forall (x y: freg), {x=y} + {x<>y}.	Lemma	arm	[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]	arm/Asm.v	freg_eq	null
crbit: Type := \| CN: crbit (*r negative ) \| CZ: crbit (*r zero ) \| CC: crbit (*r carry ) \| CV: crbit.	Inductive	arm	[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]	arm/Asm.v	crbit	Bits in the condition register.
crbit_eq: forall (x y: crbit), {x=y} + {x<>y}.	Lemma	arm	[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]	arm/Asm.v	crbit_eq	r overflow
preg: Type := \| IR: ireg -> preg (*r integer registers ) \| FR: freg -> preg (*r double-precision VFP float registers ) \| CR: crbit -> preg (*r bits in the condition register ) \| PC: preg.	Inductive	arm	[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]	arm/Asm.v	preg	We model the following registers of the ARM architecture.
preg_eq: forall (x y: preg), {x=y} + {x<>y}.	Lemma	arm	[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]	arm/Asm.v	preg_eq	null
t := preg.	Definition	arm	[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]	arm/Asm.v	t	null
eq := preg_eq.	Definition	arm	[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]	arm/Asm.v	eq	null
label := positive.	Definition	arm	[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]	arm/Asm.v	label	The instruction set. Most instructions correspond exactly to actual instructions of the ARM processor. See the ARM reference manuals for more details. Some instructions, described below, are pseudo-instructions: they expand to canned instruction sequences during the printing of the assembly code. Most instructions are common to Thumb2 and ARM classic. We use a few Thumb2-specific instructions when available, and avoid to use ARM classic features that are not in Thumb2.
shift_op : Type := \| SOimm: int -> shift_op \| SOreg: ireg -> shift_op \| SOlsl: ireg -> int -> shift_op \| SOlsr: ireg -> int -> shift_op \| SOasr: ireg -> int -> shift_op \| SOror: ireg -> int -> shift_op.	Inductive	arm	[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]	arm/Asm.v	shift_op	null
testcond : Type := \| TCeq: testcond (*r equal ) \| TCne: testcond (*r not equal ) \| TChs: testcond (*r unsigned higher or same ) \| TClo: testcond (*r unsigned lower ) \| TCmi: testcond (*r negative ) \| TCpl: testcond (*r positive ) \| TChi: testcond (*r unsigned higher ) \| TCls: testcond (*r unsigned lower or same ) \| TCge: testcond (*r signed greater or equal ) \| TClt: testcond (*r signed less than ) \| TCgt: testcond (*r signed greater ) \| TCle: testcond.	Inductive	arm	[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]	arm/Asm.v	testcond	null
code_constant: Type := \| Float32 : label -> float32 -> code_constant \| Float64 : label -> float -> code_constant \| Symbol : label -> ident -> ptrofs -> code_constant.	Inductive	arm	[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]	arm/Asm.v	code_constant	r signed less than or equal
instruction : Type := \| Padd: ireg -> ireg -> shift_op -> instruction (*r integer addition ) \| Pand: ireg -> ireg -> shift_op -> instruction (*r bitwise and ) \| Pasr: ireg -> ireg -> ireg -> instruction (*r arithmetic shift right ) \| Pb: label -> instruction (*r branch to label ) \| Pbc: testcond -> label -> instruction (*r conditional branch to label ) \| Pbsymb: ident -> signature -> instruction (*r branch to symbol ) \| Pbreg: ireg -> signature -> instruction (*r computed branch ) \| Pblsymb: ident -> signature -> instruction (*r branch and link to symbol ) \| Pblreg: ireg -> signature -> instruction (*r computed branch and link ) \| Pbic: ireg -> ireg -> shift_op -> instruction (*r bitwise bit-clear ) \| Pcmp: ireg -> shift_op -> instruction (*r integer comparison ) \| Pcmn: ireg -> shift_op -> instruction (*r integer comparison with opposite ) \| Peor: ireg -> ireg -> shift_op -> instruction (*r bitwise exclusive or ) \| Pldr: ireg -> ireg -> shift_op -> instruction (*r int32 load ) \| Pldr_a: ireg -> ireg -> shift_op -> instruction (*r any32 load to int register ) \| Pldrb: ireg -> ireg -> shift_op -> instruction (*r unsigned int8 load ) \| Pldrh: ireg -> ireg -> shift_op -> instruction (*r unsigned int16 load ) \| Pldrsb: ireg -> ireg -> shift_op -> instruction (*r signed int8 load ) \| Pldrsh: ireg -> ireg -> shift_op -> instruction (*r unsigned int16 load ) \| Plsl: ireg -> ireg -> ireg -> instruction (*r shift left ) \| Plsr: ireg -> ireg -> ireg -> instruction (*r logical shift right ) \| Pmla: ireg -> ireg -> ireg -> ireg -> instruction (*r integer multiply-add ) \| Pmov: ireg -> shift_op -> instruction (*r integer move ) \| Pmovw: ireg -> int -> instruction (*r move 16-bit immediate ) \| Pmovt: ireg -> int -> instruction (*r set high 16 bits ) \| Pmul: ireg -> ireg -> ireg -> instruction (*r integer multiplication ) \| Pmvn: ireg -> shift_op -> instruction (*r integer complement ) \| Porr: ireg -> ireg -> shift_op -> instruction (*r bitwise or ) \| Ppush: list ireg -> instruction (** push registers on the stack instruction ) \| Prsb: ireg -> ireg -> shift_op -> instruction (r integer reverse subtraction ) \| Psbfx: ireg -> ireg -> int -> int -> instruction (*r signed bitfield extract ) \| Pstr: ireg -> ireg -> shift_op -> instruction (*r int32 store ) \| Pstr_a: ireg -> ireg -> shift_op -> instruction (*r any32 store from int register ) \| Pstrb: ireg -> ireg -> shift_op -> instruction (*r int8 store ) \| Pstrh: ireg -> ireg -> shift_op -> instruction (*r int16 store ) \| Psdiv: ireg -> ireg -> ireg -> instruction (*r signed division ) \| Psmull: ireg -> ireg -> ireg -> ireg -> instruction (*r signed multiply long ) \| Psub: ireg -> ireg -> shift_op -> instruction (*r integer subtraction ) \| Pudiv: ireg -> ireg -> ireg -> instruction (*r unsigned division ) \| Pumull: ireg -> ireg -> ireg -> ireg -> instruction (*r unsigned multiply long ) \| Pfcpyd: freg -> freg -> instruction (*r float move ) \| Pfabsd: freg -> freg -> instruction (*r float absolute value ) \| Pfnegd: freg -> freg -> instruction (*r float opposite ) \| Pfaddd: freg -> freg -> freg -> instruction (*r float addition ) \| Pfdivd: freg -> freg -> freg -> instruction (*r float division ) \| Pfmuld: freg -> freg -> freg -> instruction (*r float multiplication ) \| Pfsubd: freg -> freg -> freg -> instruction (*r float subtraction ) \| Pflid: freg -> float -> instruction (*r load float constant ) \| Pfcmpd: freg -> freg -> instruction (*r float comparison ) \| Pfcmpzd: freg -> instruction (*r float comparison with 0.0 ) ...	Inductive	arm	[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]	arm/Asm.v	instruction	null
code := list instruction.	Definition	arm	[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]	arm/Asm.v	code	The pseudo-instructions are the following: - [Plabel]: define a code label at the current program point. - [Ploadsymbol]: load the address of a symbol in an integer register. Expands to a load from an address in the constant data section initialized with the symbol value: << ldr rdst, lbl .const_data lbl: .word symbol .text >> Initialized data in the constant data section are not modeled here, which is why we use a pseudo-instruction for this purpose. - [Pallocframe sz pos]: in the formal semantics, this pseudo-instruction allocates a memory block with bounds [0] and [sz], stores the value of the stack pointer at offset [pos] in this block, and sets the stack pointer to the address of the bottom of this block. In the printed ASM assembly code, this allocation is: << mov r10, sp sub sp, sp, #sz str r10, [sp, #pos] >> This cannot be expressed in our memory model, which does not reflect the fact that stack frames are adjacent and allocated/freed following a stack discipline. - [Pfreeframe sz pos]: in the formal semantics, this pseudo-instruction reads the word at [pos] of the block pointed by the stack pointer, frees this block, and sets the stack pointer to the value read. In the printed ASM assembly code, this freeing is just a load of register [sp] relative to [sp] itself: << ldr sp, [sp, #pos] >> Again, our memory model cannot comprehend that this operation frees (logically) the current stack frame. - [Pbtbl reg table]: this is a N-way branch, implemented via a jump table as follows: << ldr pc, [pc, reg] mov r0, r0 (* no-op
function : Type := mkfunction { fn_sig: signature; fn_code: code }.	Record	arm	[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]	arm/Asm.v	function	null
fundef := AST.fundef function.	Definition	arm	[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]	arm/Asm.v	fundef	null
program := AST.program fundef unit.	Definition	arm	[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]	arm/Asm.v	program	null
regset := Pregmap.t val.	Definition	arm	[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]	arm/Asm.v	regset	The semantics operates over a single mapping from registers (type [preg]) to values. We maintain (but do not enforce) the convention that integer registers are mapped to values of type [Tint], float registers to values of type [Tfloat], and condition bits to either [Vzero] or [Vone].
genv := Genv.t fundef unit.	Definition	arm	[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]	arm/Asm.v	genv	null
undef_regs (l: list preg) (rs: regset) : regset := match l with \| nil => rs \| r :: l' => undef_regs l' (rs#r <- Vundef) end.	Fixpoint	arm	[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]	arm/Asm.v	undef_regs	Undefining some registers
undef_flags (rs: regset) : regset := fun r => match r with CR _ => Vundef \| _ => rs r end.	Definition	arm	[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]	arm/Asm.v	undef_flags	Undefining the condition codes
set_pair (p: rpair preg) (v: val) (rs: regset) : regset := match p with \| One r => rs#r <- v \| Twolong rhi rlo => rs#rhi <- (Val.hiword v) #rlo <- (Val.loword v) end.	Definition	arm	[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]	arm/Asm.v	set_pair	Assigning a register pair
set_res (res: builtin_res preg) (v: val) (rs: regset) : regset := match res with \| BR r => rs#r <- v \| BR_none => rs \| BR_splitlong hi lo => set_res lo (Val.loword v) (set_res hi (Val.hiword v) rs) end.	Fixpoint	arm	[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]	arm/Asm.v	set_res	Assigning the result of a builtin

eval_shl: binary_constructor_sound shl Val.shl.

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_shl

General shifts

eval_shr: binary_constructor_sound shr Val.shr.

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_shr

null

eval_shru: binary_constructor_sound shru Val.shru.

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_shru

null

eval_negf: unary_constructor_sound negf Val.negf.

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_negf

Floating-point operations

eval_absf: unary_constructor_sound absf Val.absf.

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_absf

null

eval_addf: binary_constructor_sound addf Val.addf.

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_addf

null

eval_subf: binary_constructor_sound subf Val.subf.

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_subf

null

eval_mulf: binary_constructor_sound mulf Val.mulf.

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_mulf

null

eval_negfs: unary_constructor_sound negfs Val.negfs.

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_negfs

null

eval_absfs: unary_constructor_sound absfs Val.absfs.

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_absfs

null

eval_addfs: binary_constructor_sound addfs Val.addfs.

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_addfs

null

eval_subfs: binary_constructor_sound subfs Val.subfs.

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_subfs

null

eval_mulfs: binary_constructor_sound mulfs Val.mulfs.

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_mulfs

null

eval_compimm: forall le c a n2 x, eval_expr ge sp e m le a x -> exists v, eval_expr ge sp e m le (compimm default intsem c a n2) v /\ Val.lessdef (sem c x (Vint n2)) v.

Lemma

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_compimm

null

eval_compimm_swap: forall le c a n2 x, eval_expr ge sp e m le a x -> exists v, eval_expr ge sp e m le (compimm default intsem (swap_comparison c) a n2) v /\ Val.lessdef (sem c (Vint n2) x) v.

Lemma

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_compimm_swap

null

eval_comp: forall c, binary_constructor_sound (comp c) (Val.cmp c).

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_comp

null

eval_compu: forall c, binary_constructor_sound (compu c) (Val.cmpu (Mem.valid_pointer m) c).

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_compu

null

eval_compf: forall c, binary_constructor_sound (compf c) (Val.cmpf c).

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_compf

null

eval_compfs: forall c, binary_constructor_sound (compfs c) (Val.cmpfs c).

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_compfs

null

eval_singleoffloat: unary_constructor_sound singleoffloat Val.singleoffloat.

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_singleoffloat

Floating-point conversions

eval_floatofsingle: unary_constructor_sound floatofsingle Val.floatofsingle.

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_floatofsingle

null

eval_intoffloat: forall le a x y, eval_expr ge sp e m le a x -> Val.intoffloat x = Some y -> exists v, eval_expr ge sp e m le (intoffloat a) v /\ Val.lessdef y v.

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_intoffloat

null

eval_floatofint: forall le a x y, eval_expr ge sp e m le a x -> Val.floatofint x = Some y -> exists v, eval_expr ge sp e m le (floatofint a) v /\ Val.lessdef y v.

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_floatofint

null

eval_intuoffloat: forall le a x y, eval_expr ge sp e m le a x -> Val.intuoffloat x = Some y -> exists v, eval_expr ge sp e m le (intuoffloat a) v /\ Val.lessdef y v.

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_intuoffloat

null

eval_floatofintu: forall le a x y, eval_expr ge sp e m le a x -> Val.floatofintu x = Some y -> exists v, eval_expr ge sp e m le (floatofintu a) v /\ Val.lessdef y v.

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_floatofintu

null

eval_intofsingle: forall le a x y, eval_expr ge sp e m le a x -> Val.intofsingle x = Some y -> exists v, eval_expr ge sp e m le (intofsingle a) v /\ Val.lessdef y v.

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_intofsingle

null

eval_singleofint: forall le a x y, eval_expr ge sp e m le a x -> Val.singleofint x = Some y -> exists v, eval_expr ge sp e m le (singleofint a) v /\ Val.lessdef y v.

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_singleofint

null

eval_intuofsingle: forall le a x y, eval_expr ge sp e m le a x -> Val.intuofsingle x = Some y -> exists v, eval_expr ge sp e m le (intuofsingle a) v /\ Val.lessdef y v.

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_intuofsingle

null

eval_singleofintu: forall le a x y, eval_expr ge sp e m le a x -> Val.singleofintu x = Some y -> exists v, eval_expr ge sp e m le (singleofintu a) v /\ Val.lessdef y v.

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_singleofintu

null

eval_select: forall le ty cond al vl a1 v1 a2 v2, select_supported ty = true -> eval_exprlist ge sp e m le al vl -> eval_expr ge sp e m le a1 v1 -> eval_expr ge sp e m le a2 v2 -> exists v, eval_expr ge sp e m le (select ty cond al a1 a2) v /\ Val.lessdef (Val.select (eval_condition cond vl m) v1 v2 ty) v.

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_select

Selection

eval_addressing: forall le chunk a v b ofs, eval_expr ge sp e m le a v -> v = Vptr b ofs -> match addressing chunk a with (mode, args) => exists vl, eval_exprlist ge sp e m le args vl /\ eval_addressing ge sp mode vl = Some v end.

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_addressing

Addressing modes

eval_builtin_arg: forall a v, eval_expr ge sp e m nil a v -> CminorSel.eval_builtin_arg ge sp e m (builtin_arg a) v.

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_builtin_arg

Builtins

eval_platform_builtin: forall bf al a vl v le, platform_builtin bf al = Some a -> eval_exprlist ge sp e m le al vl -> platform_builtin_sem bf vl = Some v -> exists v', eval_expr ge sp e m le a v' /\ Val.lessdef v v'.

Theorem

aarch64

[ "Coqlib", "Zbits", "AST", "Integers", "Floats", "Values", "Memory", "Builtins", "Globalenvs", "Cminor", "Op", "CminorSel", "SelectOp" ]

aarch64/SelectOpproof.v

eval_platform_builtin

Platform-specific known builtins

fe_ofs_arg := 0.

Definition

aarch64

[ "Coqlib", "AST", "Memory", "Separation", "Bounds" ]

aarch64/Stacklayout.v

fe_ofs_arg

The general shape of activation records is as follows, from bottom (lowest offsets) to top: - Space for outgoing arguments to function calls. - Back link to parent frame - Return address - Saved values of callee-save registers used by the function. - Local stack slots. - Space for the stack-allocated data declared in Cminor. The stack pointer is kept 16-aligned.

make_env (b: bounds) : frame_env := let olink := align (4 * b.(bound_outgoing)) 8 in (* back link *) let oretaddr := olink + 8 in (* return address *) let ocs := oretaddr + 8 in (* callee-saves *) let ol := align (size_callee_save_area b ocs) 8 in (* locals *) let ostkdata := align (ol + 4 * b.(bound_local)) 8 in (* stack data *) let sz := align (ostkdata + b.(bound_stack_data)) 16 in {| fe_size := sz; fe_ofs_link := olink; fe_ofs_retaddr := oretaddr; fe_ofs_local := ol; fe_ofs_callee_save := ocs; fe_stack_data := ostkdata; fe_used_callee_save := b.(used_callee_save) |}.

Definition

aarch64

[ "Coqlib", "AST", "Memory", "Separation", "Bounds" ]

aarch64/Stacklayout.v

make_env

null

frame_env_separated: forall b sp m P, let fe := make_env b in m |= range sp 0 (fe_stack_data fe) ** range sp (fe_stack_data fe + bound_stack_data b) (fe_size fe) ** P -> m |= range sp (fe_ofs_local fe) (fe_ofs_local fe + 4 * bound_local b) ** range sp fe_ofs_arg (fe_ofs_arg + 4 * bound_outgoing b) ** range sp (fe_ofs_link fe) (fe_ofs_link fe + size_chunk Mptr) ** range sp (fe_ofs_retaddr fe) (fe_ofs_retaddr fe + size_chunk Mptr) ** range sp (fe_ofs_callee_save fe) (size_callee_save_area b (fe_ofs_callee_save fe)) ** P.

Lemma

aarch64

[ "Coqlib", "AST", "Memory", "Separation", "Bounds" ]

aarch64/Stacklayout.v

frame_env_separated

null

frame_env_range: forall b, let fe := make_env b in 0 <= fe_stack_data fe /\ fe_stack_data fe + bound_stack_data b <= fe_size fe.

Lemma

aarch64

[ "Coqlib", "AST", "Memory", "Separation", "Bounds" ]

aarch64/Stacklayout.v

frame_env_range

null

Lemma

aarch64

[ "Coqlib", "AST", "Memory", "Separation", "Bounds" ]

aarch64/Stacklayout.v

frame_env_aligned

null

eval_static_shift (s: shift) (v: aval) (n: amount32) : aval := match s with | Slsl => shl v (I n) | Slsr => shru v (I n) | Sasr => shr v (I n) | Sror => ror v (I n) end.

Definition

aarch64

[ "Coqlib", "Compopts", "AST", "Integers", "Floats", "Values", "Memory", "Globalenvs", "Op", "RTL", "ValueDomain" ]

aarch64/ValueAOp.v

eval_static_shift

Value analysis for AArch64 operators

eval_static_shiftl (s: shift) (v: aval) (n: amount64) : aval := match s with | Slsl => shll v (I n) | Slsr => shrlu v (I n) | Sasr => shrl v (I n) | Sror => rorl v (I n) end.

Definition

aarch64

[ "Coqlib", "Compopts", "AST", "Integers", "Floats", "Values", "Memory", "Globalenvs", "Op", "RTL", "ValueDomain" ]

aarch64/ValueAOp.v

eval_static_shiftl

null

eval_static_extend (x: extension) (v: aval) (n: amount64) : aval := shll (match x with Xsgn32 => longofint v | Xuns32 => longofintu v end) (I n).

Definition

aarch64

[ "Coqlib", "Compopts", "AST", "Integers", "Floats", "Values", "Memory", "Globalenvs", "Op", "RTL", "ValueDomain" ]

aarch64/ValueAOp.v

eval_static_extend

null

eval_static_condition (cond: condition) (vl: list aval): abool := match cond, vl with | Ccomp c, v1 :: v2 :: nil => cmp_bool c v1 v2 | Ccompu c, v1 :: v2 :: nil => cmpu_bool c v1 v2 | Ccompimm c n, v1 :: nil => cmp_bool c v1 (I n) | Ccompuimm c n, v1 :: nil => cmpu_bool c v1 (I n) | Ccompshift c s a, v1 :: v2 :: nil => cmp_bool c v1 (eval_static_shift s v2 a) | Ccompushift c s a, v1 :: v2 :: nil => cmpu_bool c v1 (eval_static_shift s v2 a) | Cmaskzero m, v1 :: nil => maskzero v1 m | Cmasknotzero m, v1 :: nil => cnot (maskzero v1 m) | Ccompl c, v1 :: v2 :: nil => cmpl_bool c v1 v2 | Ccomplu c, v1 :: v2 :: nil => cmplu_bool c v1 v2 | Ccomplimm c n, v1 :: nil => cmpl_bool c v1 (L n) | Ccompluimm c n, v1 :: nil => cmplu_bool c v1 (L n) | Ccomplshift c s a, v1 :: v2 :: nil => cmpl_bool c v1 (eval_static_shiftl s v2 a) | Ccomplushift c s a, v1 :: v2 :: nil => cmplu_bool c v1 (eval_static_shiftl s v2 a) | Cmasklzero m, v1 :: nil => cmpl_bool Ceq (andl v1 (L m)) (L Int64.zero) | Cmasklnotzero m, v1 :: nil => cmpl_bool Cne (andl v1 (L m)) (L Int64.zero) | Ccompf c, v1 :: v2 :: nil => cmpf_bool c v1 v2 | Cnotcompf c, v1 :: v2 :: nil => cnot (cmpf_bool c v1 v2) | Ccompfzero c, v1 :: nil => cmpf_bool c v1 (F Float.zero) | Cnotcompfzero c, v1 :: nil => cnot (cmpf_bool c v1 (F Float.zero)) | Ccompfs c, v1 :: v2 :: nil => cmpfs_bool c v1 v2 | Cnotcompfs c, v1 :: v2 :: nil => cnot (cmpfs_bool c v1 v2) | Ccompfszero c, v1 :: nil => cmpfs_bool c v1 (FS Float32.zero) | Cnotcompfszero c, v1 :: nil => cnot (cmpfs_bool c v1 (FS Float32.zero)) | _, _ => Bnone end.

Definition

aarch64

[ "Coqlib", "Compopts", "AST", "Integers", "Floats", "Values", "Memory", "Globalenvs", "Op", "RTL", "ValueDomain" ]

aarch64/ValueAOp.v

eval_static_condition

null

eval_static_addressing (addr: addressing) (vl: list aval): aval := match addr, vl with | Aindexed n, v1 :: nil => addl v1 (L n) | Aindexed2, v1 :: v2 :: nil => addl v1 v2 | Aindexed2shift a, v1 :: v2 :: nil => addl v1 (shll v2 (I a)) | Aindexed2ext x a, v1 :: v2 :: nil => addl v1 (eval_static_extend x v2 a) | Aglobal s ofs, nil => Ptr (Gl s ofs) | Ainstack ofs, nil => Ptr (Stk ofs) | _, _ => Vbot end.

Definition

aarch64

[ "Coqlib", "Compopts", "AST", "Integers", "Floats", "Values", "Memory", "Globalenvs", "Op", "RTL", "ValueDomain" ]

aarch64/ValueAOp.v

eval_static_addressing

null

eval_static_operation (op: operation) (vl: list aval): aval := match op, vl with | Omove, v1::nil => v1 | Ointconst n, nil => I n | Olongconst n, nil => L n | Ofloatconst n, nil => if propagate_float_constants tt then F n else ntop | Osingleconst n, nil => if propagate_float_constants tt then FS n else ntop | Oaddrsymbol id ofs, nil => Ptr (Gl id ofs) | Oaddrstack ofs, nil => Ptr (Stk ofs) | Oshift s a, v1::nil => eval_static_shift s v1 a | Oadd, v1::v2::nil => add v1 v2 | Oaddshift s a, v1::v2::nil => add v1 (eval_static_shift s v2 a) | Oaddimm n, v1::nil => add v1 (I n) | Oneg, v1::nil => neg v1 | Onegshift s a, v1::nil => neg (eval_static_shift s v1 a) | Osub, v1::v2::nil => sub v1 v2 | Osubshift s a, v1::v2::nil => sub v1 (eval_static_shift s v2 a) | Omul, v1::v2::nil => mul v1 v2 | Omuladd, v1::v2::v3::nil => add v1 (mul v2 v3) | Omulsub, v1::v2::v3::nil => sub v1 (mul v2 v3) | Odiv, v1::v2::nil => divs v1 v2 | Odivu, v1::v2::nil => divu v1 v2 | Oand, v1::v2::nil => and v1 v2 | Oandshift s a, v1::v2::nil => and v1 (eval_static_shift s v2 a) | Oandimm n, v1::nil => and v1 (I n) | Oor, v1::v2::nil => or v1 v2 | Oorshift s a, v1::v2::nil => or v1 (eval_static_shift s v2 a) | Oorimm n, v1::nil => or v1 (I n) | Oxor, v1::v2::nil => xor v1 v2 | Oxorshift s a, v1::v2::nil => xor v1 (eval_static_shift s v2 a) | Oxorimm n, v1::nil => xor v1 (I n) | Onot, v1::nil => notint v1 | Onotshift s a, v1::nil => notint (eval_static_shift s v1 a) | Obic, v1::v2::nil => and v1 (notint v2) | Obicshift s a, v1::v2::nil => and v1 (notint (eval_static_shift s v2 a)) | Oorn, v1::v2::nil => or v1 (notint v2) | Oornshift s a, v1::v2::nil => or v1 (notint (eval_static_shift s v2 a)) | Oeqv, v1::v2::nil => xor v1 (notint v2) | Oeqvshift s a, v1::v2::nil => xor v1 (notint (eval_static_shift s v2 a)) | Oshl, v1::v2::nil => shl v1 v2 | Oshr, v1::v2::nil => shr v1 v2 | Oshru, v1::v2::nil => shru v1 v2 | Oshrximm n, v1::nil => shrx v1 (I n) | Ozext s, v1::nil => zero_ext s v1 | Osext s, v1::nil => sign_ext s v1 | Oshlzext s a, v1::nil => shl (zero_ext s v1) (I a) | Oshlsext s a, v1::nil => shl (sign_ext s v1) (I a) | Ozextshr a s, v1::nil => zero_ext s (shru v1 (I a)) | Osextshr a s, v1::nil => sign_ext s (shr v1 (I a)) | Oshiftl s a, v1::nil => eval_static_shiftl s v1 a | Oextend x a, v1::nil => eval_static_extend x v1 a ...

Definition

aarch64

[ "Coqlib", "Compopts", "AST", "Integers", "Floats", "Values", "Memory", "Globalenvs", "Op", "RTL", "ValueDomain" ]

aarch64/ValueAOp.v

eval_static_operation

null

eval_static_shift_sound: forall v av s n, vmatch bc v av -> vmatch bc (eval_shift s v n) (eval_static_shift s av n).

Lemma

aarch64

[ "Coqlib", "Compopts", "AST", "Integers", "Floats", "Values", "Memory", "Globalenvs", "Op", "RTL", "ValueDomain" ]

aarch64/ValueAOp.v

eval_static_shift_sound

null

eval_static_shiftl_sound: forall v av s n, vmatch bc v av -> vmatch bc (eval_shiftl s v n) (eval_static_shiftl s av n).

Lemma

aarch64

[ "Coqlib", "Compopts", "AST", "Integers", "Floats", "Values", "Memory", "Globalenvs", "Op", "RTL", "ValueDomain" ]

aarch64/ValueAOp.v

eval_static_shiftl_sound

null

eval_static_extend_sound: forall v av x n, vmatch bc v av -> vmatch bc (eval_extend x v n) (eval_static_extend x av n).

Lemma

aarch64

[ "Coqlib", "Compopts", "AST", "Integers", "Floats", "Values", "Memory", "Globalenvs", "Op", "RTL", "ValueDomain" ]

aarch64/ValueAOp.v

eval_static_extend_sound

null

eval_static_condition_sound: forall cond vargs m aargs, list_forall2 (vmatch bc) vargs aargs -> cmatch (eval_condition cond vargs m) (eval_static_condition cond aargs).

Theorem

aarch64

[ "Coqlib", "Compopts", "AST", "Integers", "Floats", "Values", "Memory", "Globalenvs", "Op", "RTL", "ValueDomain" ]

aarch64/ValueAOp.v

eval_static_condition_sound

null

symbol_address_sound: forall id ofs, vmatch bc (Genv.symbol_address ge id ofs) (Ptr (Gl id ofs)).

Lemma

aarch64

[ "Coqlib", "Compopts", "AST", "Integers", "Floats", "Values", "Memory", "Globalenvs", "Op", "RTL", "ValueDomain" ]

aarch64/ValueAOp.v

symbol_address_sound

null

symbol_address_sound_2: forall id ofs, vmatch bc (Genv.symbol_address ge id ofs) (Ifptr (Gl id ofs)).

Lemma

aarch64

[ "Coqlib", "Compopts", "AST", "Integers", "Floats", "Values", "Memory", "Globalenvs", "Op", "RTL", "ValueDomain" ]

aarch64/ValueAOp.v

symbol_address_sound_2

null

eval_static_addressing_sound: forall addr vargs vres aargs, eval_addressing ge (Vptr sp Ptrofs.zero) addr vargs = Some vres -> list_forall2 (vmatch bc) vargs aargs -> vmatch bc vres (eval_static_addressing addr aargs).

Theorem

aarch64

[ "Coqlib", "Compopts", "AST", "Integers", "Floats", "Values", "Memory", "Globalenvs", "Op", "RTL", "ValueDomain" ]

aarch64/ValueAOp.v

eval_static_addressing_sound

null

eval_static_operation_sound: forall op vargs m vres aargs, eval_operation ge (Vptr sp Ptrofs.zero) op vargs m = Some vres -> list_forall2 (vmatch bc) vargs aargs -> vmatch bc vres (eval_static_operation op aargs).

Theorem

aarch64

[ "Coqlib", "Compopts", "AST", "Integers", "Floats", "Values", "Memory", "Globalenvs", "Op", "RTL", "ValueDomain" ]

aarch64/ValueAOp.v

eval_static_operation_sound

null

ptr64 := false.

Definition

arm

[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]

arm/Archi.v

ptr64

null

big_endian: bool.

Parameter

arm

[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]

arm/Archi.v

big_endian

null

align_int64 := 8%Z.

Definition

arm

[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]

arm/Archi.v

align_int64

null

align_float64 := 8%Z.

Definition

arm

[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]

arm/Archi.v

align_float64

null

splitlong := true.

Definition

arm

[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]

arm/Archi.v

splitlong

null

splitlong_ptr32: splitlong = true -> ptr64 = false.

Lemma

arm

[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]

arm/Archi.v

splitlong_ptr32

null

default_nan_64 := (false, iter_nat 51 _ xO xH).

Definition

arm

[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]

arm/Archi.v

default_nan_64

null

default_nan_32 := (false, iter_nat 22 _ xO xH).

Definition

arm

[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]

arm/Archi.v

default_nan_32

null

choose_nan (is_signaling: positive -> bool) (default: bool * positive) (l0: list (bool * positive)) : bool * positive := let fix choose_snan (l1: list (bool * positive)) := match l1 with | nil => match l0 with nil => default | n :: _ => n end | ((s, p) as n) :: l1 => if is_signaling p then n else choose_snan l1 end in choose_snan l0.

Definition

arm

[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]

arm/Archi.v

choose_nan

Choose the first signaling NaN, if any; otherwise choose the first NaN; otherwise use default.

choose_nan_idem: forall is_signaling default n, choose_nan is_signaling default (n :: n :: nil) = choose_nan is_signaling default (n :: nil).

Lemma

arm

[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]

arm/Archi.v

choose_nan_idem

null

choose_nan_64 := choose_nan (fun p => negb (Pos.testbit p 51)) default_nan_64.

Definition

arm

[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]

arm/Archi.v

choose_nan_64

null

choose_nan_32 := choose_nan (fun p => negb (Pos.testbit p 22)) default_nan_32.

Definition

arm

[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]

arm/Archi.v

choose_nan_32

null

choose_nan_64_idem: forall n, choose_nan_64 (n :: n :: nil) = choose_nan_64 (n :: nil).

Lemma

arm

[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]

arm/Archi.v

choose_nan_64_idem

null

choose_nan_32_idem: forall n, choose_nan_32 (n :: n :: nil) = choose_nan_32 (n :: nil).

Lemma

arm

[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]

arm/Archi.v

choose_nan_32_idem

null

fma_order {A: Type} (x y z: A) := (z, x, y).

Definition

arm

[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]

arm/Archi.v

fma_order

null

fma_invalid_mul_is_nan := true.

Definition

arm

[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]

arm/Archi.v

fma_invalid_mul_is_nan

null

float_of_single_preserves_sNaN := false.

Definition

arm

[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]

arm/Archi.v

float_of_single_preserves_sNaN

null

float_conversion_default_nan := false.

Definition

arm

[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]

arm/Archi.v

float_conversion_default_nan

null

abi_kind := Softfloat | Hardfloat.

Inductive

arm

[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]

arm/Archi.v

abi_kind

Which ABI to use: either the standard ARM EABI with floats passed in integer registers, or the "hardfloat" variant of the EABI that uses FP registers instead.

abi: abi_kind.

Parameter

arm

[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]

arm/Archi.v

abi

null

thumb2_support: bool.

Parameter

arm

[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]

arm/Archi.v

thumb2_support

Whether instructions added with Thumb2 are supported. True for ARMv6T2 and above.

hardware_idiv : unit -> bool.

Parameter

arm

[ "Coq.ZArith", "Coq.List", "Flocq.Binary", "Flocq.Bits" ]

arm/Archi.v

hardware_idiv

Whether the hardware supports sdiv and udiv

Inductive

arm

[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]

arm/Asm.v

ireg

Integer registers, floating-point registers.

Inductive

arm

[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]

arm/Asm.v

freg

null

Inductive

arm

[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]

arm/Asm.v

sreg

null

ireg_eq: forall (x y: ireg), {x=y} + {x<>y}.

Lemma

arm

[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]

arm/Asm.v

ireg_eq

null

freg_eq: forall (x y: freg), {x=y} + {x<>y}.

Lemma

arm

[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]

arm/Asm.v

freg_eq

null

crbit: Type := | CN: crbit (**r negative *) | CZ: crbit (**r zero *) | CC: crbit (**r carry *) | CV: crbit.

Inductive

arm

[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]

arm/Asm.v

crbit

Bits in the condition register.

crbit_eq: forall (x y: crbit), {x=y} + {x<>y}.

Lemma

arm

[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]

arm/Asm.v

crbit_eq

r overflow

preg: Type := | IR: ireg -> preg (**r integer registers *) | FR: freg -> preg (**r double-precision VFP float registers *) | CR: crbit -> preg (**r bits in the condition register *) | PC: preg.

Inductive

arm

[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]

arm/Asm.v

preg

We model the following registers of the ARM architecture.

preg_eq: forall (x y: preg), {x=y} + {x<>y}.

Lemma

arm

[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]

arm/Asm.v

preg_eq

null

t := preg.

Definition

arm

[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]

arm/Asm.v

t

null

eq := preg_eq.

Definition

arm

[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]

arm/Asm.v

eq

null

label := positive.

Definition

arm

[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]

arm/Asm.v

label

The instruction set. Most instructions correspond exactly to actual instructions of the ARM processor. See the ARM reference manuals for more details. Some instructions, described below, are pseudo-instructions: they expand to canned instruction sequences during the printing of the assembly code. Most instructions are common to Thumb2 and ARM classic. We use a few Thumb2-specific instructions when available, and avoid to use ARM classic features that are not in Thumb2.

Inductive

arm

[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]

arm/Asm.v

shift_op

null

Inductive

arm

[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]

arm/Asm.v

testcond

null

code_constant: Type := | Float32 : label -> float32 -> code_constant | Float64 : label -> float -> code_constant | Symbol : label -> ident -> ptrofs -> code_constant.

Inductive

arm

[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]

arm/Asm.v

code_constant

r signed less than or equal

instruction : Type := | Padd: ireg -> ireg -> shift_op -> instruction (**r integer addition *) | Pand: ireg -> ireg -> shift_op -> instruction (**r bitwise and *) | Pasr: ireg -> ireg -> ireg -> instruction (**r arithmetic shift right *) | Pb: label -> instruction (**r branch to label *) | Pbc: testcond -> label -> instruction (**r conditional branch to label *) | Pbsymb: ident -> signature -> instruction (**r branch to symbol *) | Pbreg: ireg -> signature -> instruction (**r computed branch *) | Pblsymb: ident -> signature -> instruction (**r branch and link to symbol *) | Pblreg: ireg -> signature -> instruction (**r computed branch and link *) | Pbic: ireg -> ireg -> shift_op -> instruction (**r bitwise bit-clear *) | Pcmp: ireg -> shift_op -> instruction (**r integer comparison *) | Pcmn: ireg -> shift_op -> instruction (**r integer comparison with opposite *) | Peor: ireg -> ireg -> shift_op -> instruction (**r bitwise exclusive or *) | Pldr: ireg -> ireg -> shift_op -> instruction (**r int32 load *) | Pldr_a: ireg -> ireg -> shift_op -> instruction (**r any32 load to int register *) | Pldrb: ireg -> ireg -> shift_op -> instruction (**r unsigned int8 load *) | Pldrh: ireg -> ireg -> shift_op -> instruction (**r unsigned int16 load *) | Pldrsb: ireg -> ireg -> shift_op -> instruction (**r signed int8 load *) | Pldrsh: ireg -> ireg -> shift_op -> instruction (**r unsigned int16 load *) | Plsl: ireg -> ireg -> ireg -> instruction (**r shift left *) | Plsr: ireg -> ireg -> ireg -> instruction (**r logical shift right *) | Pmla: ireg -> ireg -> ireg -> ireg -> instruction (**r integer multiply-add *) | Pmov: ireg -> shift_op -> instruction (**r integer move *) | Pmovw: ireg -> int -> instruction (**r move 16-bit immediate *) | Pmovt: ireg -> int -> instruction (**r set high 16 bits *) | Pmul: ireg -> ireg -> ireg -> instruction (**r integer multiplication *) | Pmvn: ireg -> shift_op -> instruction (**r integer complement *) | Porr: ireg -> ireg -> shift_op -> instruction (**r bitwise or *) | Ppush: list ireg -> instruction (** push registers on the stack instruction *) | Prsb: ireg -> ireg -> shift_op -> instruction (**r integer reverse subtraction *) | Psbfx: ireg -> ireg -> int -> int -> instruction (**r signed bitfield extract *) | Pstr: ireg -> ireg -> shift_op -> instruction (**r int32 store *) | Pstr_a: ireg -> ireg -> shift_op -> instruction (**r any32 store from int register *) | Pstrb: ireg -> ireg -> shift_op -> instruction (**r int8 store *) | Pstrh: ireg -> ireg -> shift_op -> instruction (**r int16 store *) | Psdiv: ireg -> ireg -> ireg -> instruction (**r signed division *) | Psmull: ireg -> ireg -> ireg -> ireg -> instruction (**r signed multiply long *) | Psub: ireg -> ireg -> shift_op -> instruction (**r integer subtraction *) | Pudiv: ireg -> ireg -> ireg -> instruction (**r unsigned division *) | Pumull: ireg -> ireg -> ireg -> ireg -> instruction (**r unsigned multiply long *) | Pfcpyd: freg -> freg -> instruction (**r float move *) | Pfabsd: freg -> freg -> instruction (**r float absolute value *) | Pfnegd: freg -> freg -> instruction (**r float opposite *) | Pfaddd: freg -> freg -> freg -> instruction (**r float addition *) | Pfdivd: freg -> freg -> freg -> instruction (**r float division *) | Pfmuld: freg -> freg -> freg -> instruction (**r float multiplication *) | Pfsubd: freg -> freg -> freg -> instruction (**r float subtraction *) | Pflid: freg -> float -> instruction (**r load float constant *) | Pfcmpd: freg -> freg -> instruction (**r float comparison *) | Pfcmpzd: freg -> instruction (**r float comparison with 0.0 *) ...

Inductive

arm

[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]

arm/Asm.v

instruction

null

code := list instruction.

Definition

arm

[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]

arm/Asm.v

code

The pseudo-instructions are the following: - [Plabel]: define a code label at the current program point. - [Ploadsymbol]: load the address of a symbol in an integer register. Expands to a load from an address in the constant data section initialized with the symbol value: << ldr rdst, lbl .const_data lbl: .word symbol .text >> Initialized data in the constant data section are not modeled here, which is why we use a pseudo-instruction for this purpose. - [Pallocframe sz pos]: in the formal semantics, this pseudo-instruction allocates a memory block with bounds [0] and [sz], stores the value of the stack pointer at offset [pos] in this block, and sets the stack pointer to the address of the bottom of this block. In the printed ASM assembly code, this allocation is: << mov r10, sp sub sp, sp, #sz str r10, [sp, #pos] >> This cannot be expressed in our memory model, which does not reflect the fact that stack frames are adjacent and allocated/freed following a stack discipline. - [Pfreeframe sz pos]: in the formal semantics, this pseudo-instruction reads the word at [pos] of the block pointed by the stack pointer, frees this block, and sets the stack pointer to the value read. In the printed ASM assembly code, this freeing is just a load of register [sp] relative to [sp] itself: << ldr sp, [sp, #pos] >> Again, our memory model cannot comprehend that this operation frees (logically) the current stack frame. - [Pbtbl reg table]: this is a N-way branch, implemented via a jump table as follows: << ldr pc, [pc, reg] mov r0, r0 (* no-op

function : Type := mkfunction { fn_sig: signature; fn_code: code }.

Record

arm

[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]

arm/Asm.v

function

null

fundef := AST.fundef function.

Definition

arm

[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]

arm/Asm.v

fundef

null

program := AST.program fundef unit.

Definition

arm

[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]

arm/Asm.v

program

null

regset := Pregmap.t val.

Definition

arm

[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]

arm/Asm.v

regset

The semantics operates over a single mapping from registers (type [preg]) to values. We maintain (but do not enforce) the convention that integer registers are mapped to values of type [Tint], float registers to values of type [Tfloat], and condition bits to either [Vzero] or [Vone].

genv := Genv.t fundef unit.

Definition

arm

[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]

arm/Asm.v

genv

null

undef_regs (l: list preg) (rs: regset) : regset := match l with | nil => rs | r :: l' => undef_regs l' (rs#r <- Vundef) end.

Fixpoint

arm

[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]

arm/Asm.v

undef_regs

Undefining some registers

undef_flags (rs: regset) : regset := fun r => match r with CR _ => Vundef | _ => rs r end.

Definition

arm

[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]

arm/Asm.v

undef_flags

Undefining the condition codes

set_pair (p: rpair preg) (v: val) (rs: regset) : regset := match p with | One r => rs#r <- v | Twolong rhi rlo => rs#rhi <- (Val.hiword v) #rlo <- (Val.loword v) end.

Definition

arm

[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]

arm/Asm.v

set_pair

Assigning a register pair

set_res (res: builtin_res preg) (v: val) (rs: regset) : regset := match res with | BR r => rs#r <- v | BR_none => rs | BR_splitlong hi lo => set_res lo (Val.loword v) (set_res hi (Val.hiword v) rs) end.

Fixpoint

arm

[ "Coqlib", "Maps", "AST", "Integers", "Floats", "Values", "Memory", "Events", "Globalenvs", "Smallstep", "Locations", "Conventions" ]

arm/Asm.v

set_res

Assigning the result of a builtin