8bit-threshold-computer

A Turing-complete 8-bit CPU implemented entirely as threshold logic gates.

Every logic gate is a threshold neuron: output = 1 if (Σ wᵢxᵢ + b) ≥ 0 else 0

Tensors:    3,122
Parameters: 5,648

What Is This?

A complete 8-bit processor where every operation—from Boolean logic to arithmetic to control flow—is implemented using only weighted sums and step functions. No traditional gates.

Component	Specification
Registers	4 × 8-bit general purpose
Memory	256 bytes addressable
ALU	16 operations (ADD, SUB, AND, OR, XOR, NOT, SHL, SHR, INC, DEC, CMP, NEG, PASS, ZERO, ONES, NOP)
Flags	Zero, Negative, Carry, Overflow
Control	JMP, JZ, JNZ, JC, JNC, JN, JP, JV, JNV, CALL, RET, PUSH, POP

Turing complete. Verified with loops, conditionals, recursion, and self-modification.

Circuit Categories

Category	Circuits	Examples
Boolean	9	AND, OR, NOT, NAND, NOR, XOR, XNOR, IMPLIES, BIIMPLIES
Arithmetic	18	Half/full adder, 2/4/8-bit ripple carry, comparators
ALU	3	8-bit ALU, control decoder, flag computation
Combinational	10	MUX (2:1, 4:1, 8:1), DEMUX, encoders, decoders
Control Flow	16	JMP, conditional jumps, CALL, RET, PUSH, POP
Error Detection	11	Parity (XOR tree), checksum, CRC, Hamming
Modular	11	Divisibility by 2-12 (multi-layer for non-powers-of-2)
Threshold	13	k-of-n gates, majority, minority, exactly-k
Pattern	10	Popcount, leading/trailing ones, symmetry

Usage

import torch
from safetensors.torch import load_file

tensors = load_file("neural_computer.safetensors")

def heaviside(x):
    return (x >= 0).float()

# AND gate: fires when both inputs are 1
w = tensors['boolean.and.weight']  # [1, 1]
b = tensors['boolean.and.bias']    # [-2]

for a, b_in in [(0,0), (0,1), (1,0), (1,1)]:
    inp = torch.tensor([a, b_in], dtype=torch.float32)
    out = heaviside(inp @ w + b)
    print(f"AND({a}, {b_in}) = {int(out.item())}")

Verification

The model includes iron_eval.py which exhaustively tests all circuits:

python iron_eval.py
# Output: Fitness: 1.000000 (4478 tests)

Verification Status

Category	Status	Notes
Boolean gates	Coq-derived	Original formal proofs
Arithmetic	Coq-derived	Adders, comparators
ALU	Coq-derived	All 16 operations
Control flow	Coq-derived	Jumps, stack ops
Threshold	Coq-derived	k-of-n gates
Modular (mod 3,5,6,7,9,10,11,12)	Hand-verified	Multi-layer circuits added manually
Parity	Hand-verified	XOR tree structure added manually
Modular (mod 2,4,8)	Exact	Single-layer, trivial

The modular arithmetic circuits for non-powers-of-2 and the parity circuits were hand-constructed because:

Divisibility by 3, 5, etc. is not linearly separable in binary
8-bit parity (XOR of all bits) requires a tree of XOR gates

These circuits pass exhaustive testing but lack formal proofs.

Tensor Naming Convention

{category}.{circuit}[.{layer}][.{component}].{weight|bias}

Examples:
  boolean.and.weight
  boolean.xor.layer1.neuron1.weight
  arithmetic.ripplecarry8bit.fa7.ha2.sum.layer1.or.weight
  modular.mod5.layer2.eq3.weight
  error_detection.paritychecker8bit.stage2.xor1.layer1.nand.bias

Hardware Compatibility

All weights are integers. All activations are Heaviside step. Designed for:

Intel Loihi — Neuromorphic research chip
IBM TrueNorth — 1M neuron chip
BrainChip Akida — Edge neuromorphic processor

Files

File	Description
`neural_computer.safetensors`	All 1,482 circuit tensors (~152 KB)
`iron_eval.py`	Comprehensive test suite (4,416 tests)

Citation

@misc{8bit-threshold-computer,
  title={8bit-threshold-computer: A Turing-Complete Threshold Logic CPU},
  author={Norton, Charles},
  year={2025},
  howpublished={Hugging Face},
  url={https://huggingface.co/phanerozoic/8bit-threshold-computer}
}

License

MIT

phanerozoic
/

8bit-threshold-computer